the events priority in the nmpra and consumption of resources analysis on the fpga
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2018
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Abstract
The MPRA (Multi Pipeline Register Architecture) was modified and converted into n-task MPRA (nMPRA)
by replicating the pipeline registers. While the original MPRA provided hardware scheduling, the
interrupts and the events caused too long delays. The author proposes the original solutions for
the interrupts and the events treatment, which represent the author's contribution to improving
nMPRA; after the theoretical presentations of these solutions in the author's previous articles,
this paper presents the implementations of the schemes, the results of the tests and the improved
schemes. The MPRA, MPRA4 and MPRA8 implementations on FPGA (Field Programmable Gate Array) were
used to evaluate performances. A detailed analysis, partially presented in this paper, shows
other advantages: no extra software is required, the hardware implementation is simple, the
interrupts and events are similarly handled and the tasks synchronizations and communications
are completely based on hardware; MPRA has a low power consumption, even multiplied by eight
times, it is reasonably necessary memory and logic resource consumption multiplied by about
four times at MPRA4 (compared to MPRA) and by about eight times at MPRA8.
| Reference Key |
e.-e.2018advancesthe
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|---|---|
| Authors | ;CIOBANU, E.-E. |
| Journal | JMIR mHealth and uHealth |
| Year | 2018 |
| DOI |
10.4316/AECE.2018.01017
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| URL | |
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