a new systolic array algorithm and architecture for the vlsi implementation of idst based on a pseudo-band correlation structure

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ID: 176248
2017
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Abstract
In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a new efficient VLSI algorithm based on a regular and modular computational structure called pseudo-band correlation structure. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low hardware complexity and low I/O cost. A highly efficient VLSI chip can be obtained characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N, a good topology with modular, regular and local connections.
Reference Key
f.2017advancesa Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;CHIPER, D. F.;CRACAN, A.;BURDIA, D.
Journal JMIR mHealth and uHealth
Year 2017
DOI
10.4316/AECE.2017.01011
URL
http://dx.doi.org/10.4316/AECE.2017.01011
Keywords
electronics computer hardware nuclear engineeringcomputer engineering

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