An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

Clicks: 181
ID: 55829
2014
Article Quality & Performance Metrics
Overall Quality
Not rated
Combines reader engagement with the AI quality analysis. This article has not been analysed, so there is no overall score — reader engagement is measured and shown alongside.
AI Quality Assessment
Not analyzed
Readership in this journal
Popular

Ranked #116 of 127 articles by views in conference proceedings : annual international conference of the ieee engineering in medicine and biology society ieee engineering in medicine and biology society annual conference

Most read Least read

Bar heights use a square-root scale. Only the 120 most-read articles are drawn; the journal has 127 in total.

Mint this article as an NFT
Not yet minted

Create a permanent, verifiable on-chain record of this article on the Scimatic Network. The NFT is held in your Journament account, and you can withdraw it to your own wallet at any time.

5 SUSD one-off · no wallet required
Sign in to mint
Abstract
This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.
Reference Key
fang2014anconference Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Fang, Wai-Chi;Huang, Kuan-Ju;Chou, Chia-Ching;Chang, Jui-Chung;Cauwenberghs, Gert;Jung, Tzyy-Ping;
Journal conference proceedings : annual international conference of the ieee engineering in medicine and biology society ieee engineering in medicine and biology society annual conference
Year 2014
DOI
10.1109/EMBC.2014.6944463
URL
Keywords Keywords not found

Citations

No citations found. To add a citation, contact the admin at info@scimatic.org

Comments

No comments yet. Be the first to comment on this article.