Air-gap engineering enabled ultrafast 9-bit ferroelectric semi-gate transistor array for high-efficiency image denoising

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ID: 332127
2026
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Abstract
Abstract The insufficient lateral electric field gradient limits the programming/erasing speed of conventional semi-floating gate transistors, while charge leakage leads to poor data retention and compromised operating characteristics. Here we design a ferroelectric semi-gate (FSG) transistor featuring a triangular air gap adjacent to the drain region. The device exhibits an as-programmed on–off ratio exceeding 107, remaining above 105 after 11 weeks, and a memory window of approximately 6 V. The localized lateral electric field accelerates program and erase operations to 60 ns and 75 ns, respectively. The spontaneous polarization field of the ferroelectric HfZrO layer strengthens charge retention in the HfO2 charge-trapping layer, enabling robust nonvolatile memory performance with a retention time exceeding 106 s. This synergistic integration of air-gap engineering and ferroelectric polarization yields an optimal trade-off between speed, retention and multilevel operation. By exploiting its superior multilevel capability with 9-bit distinguishable current states, we realize Ising-model-based image denoising using a 32 × 32 transistor array. These FSG transistors show promising potential for high-speed, low-power random-access memory applications.
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Authors Chengjie Zhou, Pengcheng Zeng, Wencheng Niu, Changyan Chen, Zhenyu Yang, Rui Ying He, Zhengdao Xie, Lin Tang, Zhihao Zhang, Chang Liu, Penghui He, Qingjiang Li, Xuming Zou, Zhuojun Chen, Lei Liao, Xingqiang Liu
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Journal national science review
Year 2026
DOI
10.1093/nsr/nwag635
URL
https://doi.org/10.1093/nsr/nwag635
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