phase opposition disposition pwm strategy and hardware in the loop validation for a 3-sm modular multilevel converter

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ID: 256853
2017
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Abstract
This paper focuses on the carrier disposition Pulse Width Modulation (PWM) strategies for Modular Multilevel Converters (MMC). The authors propose a new Phase Opposition Disposition PWM (PODPWM) scheme applicable regardless of the converter’s sub-modules number. Moreover, a capacitor voltage sorting algorithm is synthesized aiming to ensure the converter’s balanced operation. Simulation results of a 3.6 MVA, 3-SM-MMC are presented and discussed. In addition, a Hardware In the Loop (HIL) validation of the proposed PODPWM has been made using Field Programmable Gate Array (FPGA) target. The actual power system (the 3-SM-MMC and the 3-phase RL load) is then replaced by its real-time emulator. The latter is interfaced to the PODPWM control under test and both are implemented and run altogether in the same Xilinx XC7Z020 Zynq FPGA device. The obtained real-time HIL emulation results are presented and compared to the offline simulation results.
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ouerdani2017journalphase Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Imen Ouerdani;Mohamed Dagbagi;Afef Bennani Ben Abdelghani;Ilhem Slama Belkhodja;Daniel Montesinos Miracle
Journal آب و فاضلاب
Year 2017
DOI
DOI not found
URL
http://journal.esrgroups.org/jes/papers/13_1_1.pdf
Keywords
pulse width modulation circulating current electronics nuclear engineering hardware in the loopelectrical engineering

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