a chaotic ip watermarking in physical layout level based on fpga

Clicks: 191
ID: 242868
2011
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Ranked #42 of 100 articles by views in molecular therapy : the journal of the american society of gene therapy

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Abstract
A new chaotic map based IP (Intellectual Property) watermarking scheme at physical design level is presented. An encrypted watermark is embedded into the physical layout of a circuit by configuring LUT (Lookup Table) as specific functions when it is placed and routed onto the FPGA (Field-Programmable Gate Array). The main contribution is the use of multiple chaotic maps in the processes of watermark design and embedding, which efficiently improves the security of watermark. A hashed chaotic sequence is used to scramble the watermark. Secondly, two pseudo-random sequences are generated by using chaotic maps. One is used to determine unused LUT locations, and the other divides the watermark into groups. The watermark identifies original owner and is difficult to detect. This scheme was tested on a Xilinx Virtex XCV600-6bg432 FPGA. The experimental results show that our method has low impact on functionality, short path delay and high robustness in comparison with other methods.
Reference Key
liang2011radioengineeringa Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;W. Liang;X. Sun;Z. Xia;D. Sun;J. Long
Journal molecular therapy : the journal of the american society of gene therapy
Year 2011
DOI
DOI not found
URL
www.radioeng.cz/fulltexts/2011/11_01_118_125.pdf
Keywords
fpga chaotic map electronics nuclear engineering ip watermarkingelectrical engineering

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