novel power reduction technique for reram with automatic avoidance circuit for wasteful overwrite

Clicks: 106
ID: 229426
2012
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Ranked #44 of 63 articles by views in anales de psicologia

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Abstract
Low-power operations can be great advantageous for ReRAM devices. However, wasteful overwriting such as the SET operation to low-resistance state (LRS) device and the RESET operation to high-resistance state (HRS) device causes not only an increase in power but also the degradation of the write cycles due to repeatedly rewriting. Thus, in this paper, we proposed a novel automatic avoidance circuit for dealing with wasteful overwriting that uses a sense amplifier and estimated the energy consumption reduction rate by conducting a circuit simulation. As a result, this circuit helped to reliably avoid the wasteful overwriting operation to reduce about 99% and 97% of wasteful energy using VSRC and CSRC, respectively.
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handa2012activenovel Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Takaya Handa;Yuhei Yoshimoto;Kazuya Nakayama;Akio Kitagawa
Journal anales de psicologia
Year 2012
DOI
10.1155/2012/181395
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