Low-Power Pedestrian Detection System on FPGA

Clicks: 158
ID: 71244
2019
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Abstract
Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.
Reference Key
ngo2019lowpowerproceedings Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Ngo, Vinh;Castells-Rufas, David;Casadevall, Arnau;Codina, Marc;Carrabina, Jordi;
Journal proceedings
Year 2019
DOI
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URL
https://www.mdpi.com/2504-3900/31/1/35
Keywords
general works

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