SiGe FinFET for practical logic libraries by mitigating local layout effect

Clicks: 213
ID: 36251
2017
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Reference Key
tsutsui2017sigedigest Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Tsutsui, G.
Journal digest of technical papers - symposium on vlsi technology
Year 2017
DOI
10.23919/VLSIT.2017.7998215
URL
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