An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

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ID: 272465
2021
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Abstract
Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance and energy simulators, our proposed L2 cache architecture supporting bypassing is shown to be effective in reducing L2 cache energy consumption and increasing overall performance of programs.
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park2021electronicsan Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Jungwoo Park;Soontae Kim;Jong-Uk Hou;Park, Jungwoo;Kim, Soontae;Hou, Jong-Uk;
Journal Electronics
Year 2021
DOI
10.3390/electronics10111328
URL
https://www.mdpi.com/2079-9292/10/11/1328
Keywords
memory computer architecture cache low-power computing multicore system

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