GaN cascode performance optimization for high efficient power applications

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ID: 270071
2016
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Abstract
GaN Cascode performance optimization for high efficient power applications is presented in this paper. Analytical equations of Cascode capacitance network (Ciss, Coss, Cgd) is demonstrated and the equations accuracy is verified through experimental measurement. Analysis shows that Cascode Cgd is determined by HV D-MISFETs Cds, LV Si FETs Cgd/Coss ratio, and extra zener diode capacitance. With low intrinsic capacitance HV D-MISFETs [1-2], proper LV Si FETs selection, and extra zener diode protection, optimization for Cascode switching figure-of-merit (FOM, Ron x Qgd) is well demonstrated. 8.8X lower switching figure-of-merit than commercial best-in-class Si SJ FETs [3] is achieved, double pulse test (DPT) and hard switching PFC system verification result all indicate that GaN Cascode is the promising solution and ready for next generation energy systems.
Reference Key
kalnitsky20162016gan Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Haw-Yun Wu,Ming-Cheng Lin,Nan-Ying Yang,C. T. Tsai,C.B. Wu,Y.S. Lin,Y. C. Chang,P. C. Chen,K. Y. Wong,M. H. Kwan,C. Y. Chan,F. W. Yao,M.W. Tsai,C. L. Yeh,R. Y. Su,J. L. Yu,F.J. Yang,J.L. Tsai,H. C. Tuan,Alex Kalnitsky;Haw-Yun Wu;Ming-Cheng Lin;Nan-Ying Yang;C. T. Tsai;C.B. Wu;Y.S. Lin;Y. C. Chang;P. C. Chen;K. Y. Wong;M. H. Kwan;C. Y. Chan;F. W. Yao;M.W. Tsai;C. L. Yeh;R. Y. Su;J. L. Yu;F.J. Yang;J.L. Tsai;H. C. Tuan;Alex Kalnitsky;
Journal 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD)
Year 2016
DOI
10.1109/ispsd.2016.7520826
URL
https://sciprofiles.com/publication/view/22b1be90a9450d4cf56d3477522974bb
Keywords
capacitance silicon energy loss switches gallium nitride field effect transistors switching loss

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