xor-free implementation of convolutional encoder for reconfigurable hardware

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ID: 223125
2016
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Abstract
This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.
Reference Key
purohit2016internationalxor-free Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Gaurav Purohit;Kota Solomon Raju;Vinod Kumar Chaubey
Journal case reports in ophthalmological medicine
Year 2016
DOI
10.1155/2016/9128683
URL
http://dx.doi.org/10.1155/2016/9128683
Keywords
computer engineering computer hardware

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