high-level synthesis under fixed-point accuracy constraint

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ID: 195335
2012
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Abstract
Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.
Reference Key
menard2012journalhigh-level Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Daniel Menard;Nicolas Herve;Olivier Sentieys;Hai-Nam Nguyen
Journal Molecular diversity
Year 2012
DOI
10.1155/2012/906350
URL
http://dx.doi.org/10.1155/2012/906350
Keywords
computer engineering computer hardware

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