an asynchronous ieee floating-point arithmetic unit

Clicks: 127
ID: 191902
2007
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Abstract
An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differentialcascode voltage switch) logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data andsingle-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit) addition/subtraction, multiplication,division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, withrounding and other operations to be handled by separate hardware or software. Division and remainderare done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptionsare noted by flags (and not trap handlers) and the output is in single-precision.Previous work on asynchronous floating-point arithmetic units have mostly focused on single operationssuch as division. This is the first work to the authors' knowledge that can perform floating-point addition,multiplication, division, and remainder using a common datapath.
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noche2007sciencean Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Joel R. Noche;Jose C. Araneta
Journal hydrology
Year 2007
DOI
DOI not found
URL
http://journals.upd.edu.ph/index.php/sciencediliman/article/view/711
Keywords
calculation timessciencescience (general)

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