ncor: an fpga-friendly nonblocking data cache for soft processors with runahead execution

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ID: 186806
2012
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Abstract
Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies. Instead, these processors use non-blocking caches to extract memory level parallelism and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. NCOR does not require CAMs and utilizes smart cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic elements.
Reference Key
aasaraai2012internationalncor: Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Kaveh Aasaraai;Andreas Moshovos
Journal case reports in ophthalmological medicine
Year 2012
DOI
10.1155/2012/915178
URL
http://dx.doi.org/10.1155/2012/915178
Keywords
computer engineering computer hardware

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