Low Resource FPGA Based Time-to-Digital Converter

Clicks: 210
ID: 13862
2016
Article Quality & Performance Metrics
Overall Quality
Not rated
Combines reader engagement with the AI quality analysis. This article has not been analysed, so there is no overall score — reader engagement is measured and shown alongside.
AI Quality Assessment
Not analyzed
Readership in this journal
Steady

Ranked #96 of 148 articles by views in adbu journal of engineering technology

Most read Least read

Bar heights use a square-root scale. Only the 120 most-read articles are drawn; the journal has 148 in total.

Mint this article as an NFT
Not yet minted

Create a permanent, verifiable on-chain record of this article on the Scimatic Network. The NFT is held in your Journament account, and you can withdraw it to your own wallet at any time.

5 SUSD one-off · no wallet required
Abstract
For the precise measurement of the time difference between the arrival of different signals coming from the different channels, the time-to-digital converter (TDC) implemented in Field Programmable Gate Array (FPGA) is a very useful device. The TDC implemented so far are  basically tapped delay lines which provides a resolution of about 10 ps however such high resolution is necessary for some specific applications. So a low resource TDC implemented in FPGA is preferred which helps to measure the time difference between the signals. Keywords: analog-to-digital converter (ADC), resolution, DPLL, clock generation, jitter
Reference Key
bhattacharyya2016lowadbu Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Ragib Nasir Ahmed, Sabyasachi Bhattacharyya, Basab B. Purkayastha, Kaustubh Bhattacharyya;
Journal adbu journal of engineering technology
Year 2016
DOI
DOI not found
URL
Keywords Keywords not found

Citations

No citations found. To add a citation, contact the admin at info@scimatic.org

No comments yet. Be the first to comment on this article.