adaptive multiclient network-on-chip memory core: hardware architecture, software abstraction layer, and application exploration

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ID: 136425
2012
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Abstract
This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC). The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.
Reference Key
ghringer2012internationaladaptive Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors ;Diana Göhringer;Lukas Meder;Stephan Werner;Oliver Oey;Jürgen Becker;Michael Hübner
Journal case reports in ophthalmological medicine
Year 2012
DOI
10.1155/2012/298561
URL
http://dx.doi.org/10.1155/2012/298561
Keywords
computer engineering computer hardware

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