Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems

Clicks: 335
ID: 111332
2012
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Abstract
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode.
Reference Key
atoche2012sensorsdual Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Alejandro Castillo Atoche;Javier Vázquez Castillo;Atoche, Alejandro Castillo;Castillo, Javier Vázquez;
Journal sensors
Year 2012
DOI
10.3390/s120302539
URL
https://www.mdpi.com/1424-8220/12/3/2539
Keywords
remote sensing fpga parallel computing super-systolic

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