Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

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ID: 108542
2012
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lee2012instructionconcurrency Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Lee, Cheng-Yu;Hung, Min-Chin;Chang, Rong-Guey;
Journal concurrency and computation: practice and experience
Year 2012
DOI
10.1002/cpe.2954
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