AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

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ID: 10629
2019
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Abstract
Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low bisection bandwidth. Fat trees are proposed to alleviate this issue by using increasingly thicker links to connect switches towards the root node. This scheme is very efficient in interconnected networks such as computer networks, which use generic switches for interconnection. In an NoC context, especially for field programmable gate arrays (FPGAs), fat trees require more complex switches as we move higher in the hierarchy. This restricts the maximum clock frequency at which the network operates and offsets the higher bandwidth achieved through using fatter links. In this paper, we discuss the implementation of a binary tree-based NoC, which achieves better bandwidth by varying the clock frequency between the switches as we move higher in the hierarchy. This scheme enables using simpler switch architecture, thus supporting higher maximum frequency of operation. The effect on bandwidth and resource requirement of this architecture is compared with other FPGA-based NoCs for different network sizes and traffic patterns.
Reference Key
kizheppatt2019asyncbtreeinternational Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Vipin, Kizheppatt;Vipin, Kizheppatt;
Journal international journal of reconfigurable computing
Year 2019
DOI
10.1155/2019/7239858
URL
https://www.hindawi.com/journals/ijrc/2019/7239858/abs/
Keywords Keywords not found

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