FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

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ID: 10628
2019
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Abstract
Recently, the Reconfigurable FSM has drawn the attention of the researchers for multistage signal processing applications. The optimal synthesis of Reconfigurable finite state machine with input multiplexing (Reconfigurable FSMIM) architecture is done by the iterative greedy heuristic based Hungarian algorithm (IGHA). The major problem concerning IGHA is the disintegration of a state encoding technique. This paper proposes the integration of IGHA with the state assignment using logarithmic barrier function based gradient descent approach to reduce the hardware consumption of Reconfigurable FSMIM. Experiments have been performed using MCNC FSM benchmarks which illustrate a significant area and speed improvement over other architectures during field programmable gate array (FPGA) implementation.
Reference Key
nitish2019fpgainternational Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Das, Nitish;P, Aruna Priya;Das, Nitish;P, Aruna Priya;
Journal international journal of reconfigurable computing
Year 2019
DOI
10.1155/2019/3727254
URL
https://www.hindawi.com/journals/ijrc/2019/3727254/abs/
Keywords Keywords not found

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