A low latency and low power indirect topology for on-chip communication.

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ID: 100054
2019
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Abstract
This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.
Reference Key
gulzari2019aplos Use this key to autocite in the manuscript while using SciMatic Manuscript Manager or Thesis Manager
Authors Gulzari, Usman Ali;Khan, Sarzamin;Sajid, Muhammad;Anjum, Sheraz;Torres, Frank Sill;Sarjoughian, Hessam;Gani, Abdullah;
Journal PloS one
Year 2019
DOI
10.1371/journal.pone.0222759
URL
Keywords
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